1. Field of the Invention
The present invention relates generally to techniques to reduce power in a processor, and, more particularly, to advantageous techniques for selectively enabling comparators in a content addressable memory (CAM) renaming register file based on known processor state.
2. Relevant Background
In order to achieve high performance program execution, a processor implementation may use a pipeline that operates at a high clock rate with short duration pipeline stages. The instruction set architecture for this type of processor may also specify a set of general purpose registers to be used by execution units as sources of data and destinations for results. Each instruction includes, as a portion of the instruction encoding, bit fields that specify the addresses of registers to be used as source or destination operands. These register specifiers are referred to as instruction register numbers (IRNs). The set of general purpose registers available for use by the execution units may vary, dependent upon the processor's operating state. For example, a program executing in a particular operating mode may be restricted to using instructions that can access only a subset of the total set of general purpose registers. The processor may also support executing instructions out of order during pipelined execution and prior to completing the instructions in program order. In order to support deep pipelines with out of order execution, a processor may implement a larger number of physical registers than can be supported by the processor's instruction set architecture. The physical registers implemented in a register file would typically be accessed by use of a physical register number (PRN) address. There are difficulties, though, with an instruction directly using a PRN address. For example, a processor supporting an instruction set architecture with an IRN address space of sixteen registers may be implemented with a PRN address space of sixty four physical registers. To resolve this difference between the IRN address space and the PRN address space, the processor may use renaming hardware to map an IRN address contained in an instruction to a physical register number (PRN) address. Such mapping can be accomplished by use of a content addressable memory (CAM) having tags, tag comparators, and data arrays. The renaming hardware may use the IRN address as a tag for a physical register stored in the CAM data array.
The problem with using CAMs for such purposes is that the CAM tag comparators in a generic CAM implementation are evaluated on every register file access. For a high performance implementation, the CAM comparators are dynamic designs and consume power as they precharge and discharge. Further, since the register file is typically a multi-ported structure, there are multiple CAM comparators on each port further increasing power drain.